Rubygems | Latest Versions for rggenhttps://rubygems.org/gems2024-01-23T12:39:20Zrggen (0.33.1)https://rubygems.org/gems/rggen/versions/0.33.12024-01-23T12:39:20ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.33.0)https://rubygems.org/gems/rggen/versions/0.33.02024-01-22T06:46:27ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.32.2)https://rubygems.org/gems/rggen/versions/0.32.22024-01-03T15:11:07ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.32.1)https://rubygems.org/gems/rggen/versions/0.32.12024-01-03T14:45:38ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.32.0)https://rubygems.org/gems/rggen/versions/0.32.02023-12-28T14:27:48ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.31.3)https://rubygems.org/gems/rggen/versions/0.31.32023-10-18T02:05:53ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.31.2)https://rubygems.org/gems/rggen/versions/0.31.22023-10-16T23:44:22ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.31.1)https://rubygems.org/gems/rggen/versions/0.31.12023-10-16T15:19:19ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.31.0)https://rubygems.org/gems/rggen/versions/0.31.02023-09-12T13:33:57ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.30.2)https://rubygems.org/gems/rggen/versions/0.30.22023-08-08T14:56:45ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.30.1)https://rubygems.org/gems/rggen/versions/0.30.12023-06-09T14:32:36ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.30.0)https://rubygems.org/gems/rggen/versions/0.30.02023-04-28T14:13:15ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.29.0)https://rubygems.org/gems/rggen/versions/0.29.02023-01-02T13:16:16ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate source code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.28.0)https://rubygems.org/gems/rggen/versions/0.28.02022-10-10T14:57:47ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.27.2)https://rubygems.org/gems/rggen/versions/0.27.22022-08-30T14:50:43ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
rggen (0.27.1)https://rubygems.org/gems/rggen/versions/0.27.12022-08-21T15:18:27ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.27.0)https://rubygems.org/gems/rggen/versions/0.27.02022-07-05T13:59:25ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.26.2)https://rubygems.org/gems/rggen/versions/0.26.22022-06-13T12:58:39ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.26.1)https://rubygems.org/gems/rggen/versions/0.26.12022-06-07T13:16:01ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.26.0)https://rubygems.org/gems/rggen/versions/0.26.02022-03-25T13:40:51ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.25.4)https://rubygems.org/gems/rggen/versions/0.25.42023-10-16T15:42:44ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.25.3)https://rubygems.org/gems/rggen/versions/0.25.32021-05-17T16:14:08ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.25.2)https://rubygems.org/gems/rggen/versions/0.25.22021-05-16T12:52:56ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.25.1)https://rubygems.org/gems/rggen/versions/0.25.12021-03-02T12:55:22ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.25.0)https://rubygems.org/gems/rggen/versions/0.25.02021-02-28T01:20:49ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.24.0)https://rubygems.org/gems/rggen/versions/0.24.02021-01-20T14:40:21ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.23.2)https://rubygems.org/gems/rggen/versions/0.23.22020-10-31T14:29:19ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.23.1)https://rubygems.org/gems/rggen/versions/0.23.12020-10-24T16:11:16ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.23.0)https://rubygems.org/gems/rggen/versions/0.23.02020-08-25T13:30:49ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.22.0)https://rubygems.org/gems/rggen/versions/0.22.02020-08-17T15:05:06ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.21.1)https://rubygems.org/gems/rggen/versions/0.21.12020-07-24T23:19:48ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.21.0)https://rubygems.org/gems/rggen/versions/0.21.02020-07-22T13:17:52ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.20.0)https://rubygems.org/gems/rggen/versions/0.20.02020-07-06T15:03:23ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.19.1)https://rubygems.org/gems/rggen/versions/0.19.12020-02-17T14:17:14ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.19.0)https://rubygems.org/gems/rggen/versions/0.19.02020-02-17T13:37:14ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.18.0)https://rubygems.org/gems/rggen/versions/0.18.02019-11-19T09:32:00ZTaichi IshitaniCode generation tool for configuration and status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to configuration and status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.17.0)https://rubygems.org/gems/rggen/versions/0.17.02019-11-13T02:45:36ZTaichi IshitaniCode generation tool for control/status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to control/status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.16.0)https://rubygems.org/gems/rggen/versions/0.16.02019-10-01T08:30:41ZTaichi IshitaniCode generation tool for control/status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to control/status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.15.0)https://rubygems.org/gems/rggen/versions/0.15.02019-09-18T16:18:12ZTaichi IshitaniCode generation tool for control/status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to control/status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.14.0)https://rubygems.org/gems/rggen/versions/0.14.02019-09-03T14:44:11ZTaichi IshitaniCode generation tool for control/status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to control/status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.13.0)https://rubygems.org/gems/rggen/versions/0.13.02019-08-28T15:41:16ZTaichi IshitaniCode generation tool for control/status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to control/status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.12.0)https://rubygems.org/gems/rggen/versions/0.12.02019-08-19T07:10:55ZTaichi IshitaniCode generation tool for control/status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to control/status registers (CSR),
e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
rggen (0.11.0)https://rubygems.org/gems/rggen/versions/0.11.02019-08-11T15:28:16ZTaichi IshitaniCode generation tool for control/status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model,
from human readable register map specifications.
rggen (0.10.0)https://rubygems.org/gems/rggen/versions/0.10.02019-07-31T15:40:01ZTaichi IshitaniCode generation tool for control/status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model,
from human readable register map documents.
rggen (0.9.0)https://rubygems.org/gems/rggen/versions/0.9.02019-07-26T16:15:15ZTaichi IshitaniCode generation tool for control/status registers
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model,
from human readable register map documents.
rggen (0.8.2)https://rubygems.org/gems/rggen/versions/0.8.22019-05-26T15:17:19ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.8.1)https://rubygems.org/gems/rggen/versions/0.8.12019-05-15T09:53:57ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.8.0)https://rubygems.org/gems/rggen/versions/0.8.02019-01-31T01:25:53ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.7.2)https://rubygems.org/gems/rggen/versions/0.7.22019-01-14T12:38:38ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.7.1)https://rubygems.org/gems/rggen/versions/0.7.12018-12-20T05:13:20ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.7.0)https://rubygems.org/gems/rggen/versions/0.7.02018-12-20T02:00:05ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.6.4)https://rubygems.org/gems/rggen/versions/0.6.42018-02-09T13:26:10ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.6.3)https://rubygems.org/gems/rggen/versions/0.6.32017-06-06T17:23:41ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.6.2)https://rubygems.org/gems/rggen/versions/0.6.22017-06-02T18:38:42ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.6.1)https://rubygems.org/gems/rggen/versions/0.6.12017-05-31T03:00:21ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.6.0)https://rubygems.org/gems/rggen/versions/0.6.02017-05-25T03:48:24ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.5.1)https://rubygems.org/gems/rggen/versions/0.5.12017-04-26T15:59:40ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, C header file, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.5.0)https://rubygems.org/gems/rggen/versions/0.5.02017-04-25T17:47:54ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.4.4)https://rubygems.org/gems/rggen/versions/0.4.42016-11-14T04:20:48ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.4.3)https://rubygems.org/gems/rggen/versions/0.4.32016-08-23T16:23:17ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.4.2)https://rubygems.org/gems/rggen/versions/0.4.22016-07-14T03:13:04ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.4.1)https://rubygems.org/gems/rggen/versions/0.4.12016-06-07T15:19:46ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.4.0)https://rubygems.org/gems/rggen/versions/0.4.02016-05-24T14:29:30ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.3.3)https://rubygems.org/gems/rggen/versions/0.3.32016-04-20T13:44:18ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.3.2)https://rubygems.org/gems/rggen/versions/0.3.22016-04-15T17:42:48ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.3.1)https://rubygems.org/gems/rggen/versions/0.3.12016-04-14T16:50:59ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
Also RgGen is customizable so you can build your specific generate tool.
rggen (0.3.0)https://rubygems.org/gems/rggen/versions/0.3.02016-04-13T15:22:29ZTaichi IshitaniCode generation tool for control registers in a SoC design.
RgGen is a code generation tool for SoC designers.
You can automatically generate soruce code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
You can also customize RgGen, so you can build your specific generation tool.