rggen 0.14.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Gemfile:
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install:
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Versions:

0.31.3 - October 18, 2023 (16 KB)
0.31.0 - September 12, 2023 (16 KB)
0.30.2 - August 08, 2023 (16 KB)
0.30.1 - June 09, 2023 (15.5 KB)
0.30.0 - April 28, 2023 (15.5 KB)
0.14.0 - September 03, 2019 (8.5 KB)

Show all versions (62 total)

Runtime Dependencies (5):

rggen-core ~> 0.14

rggen-default-register-map ~> 0.14

rggen-markdown ~> 0.13

rggen-spreadsheet-loader ~> 0.13

rggen-systemverilog ~> 0.14

Development Dependencies (1):

bundler >= 0

Show all transitive dependencies

Owners:

Pushed by:

Authors:

Taichi Ishitani

SHA 256 checksum:

d4dee516c1f51c2cb609296ed62ce807483b263cf0e8ddb1bbdeae0bf2a46b70

rggen 0.14.0

Gemfile:
= Copy to clipboard Copied!

install:
=

Versions:

Runtime Dependencies (5):

Development Dependencies (1):

Owners:

Pushed by:

Authors:

SHA 256 checksum:

Total downloads 81,969

For this version 1,646

License:
MIT

Required Ruby Version: >= 2.3

New versions require MFA: true

Links:

rggen 0.14.0

Gemfile: = Copy to clipboard Copied!

install: =

Versions:

Runtime Dependencies (5):

Development Dependencies (1):

Owners:

Pushed by:

Authors:

SHA 256 checksum:

Total downloads 81,969

For this version 1,646

License: MIT

Required Ruby Version: >= 2.3

New versions require MFA: true

Links:

Gemfile:
= Copy to clipboard Copied!

install:
=

License:
MIT