rggen 0.14.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Gemfile:
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Installeer:
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Versies:

0.33.1 - January 23, 2024 (16 KB)
0.33.0 - January 22, 2024 (16 KB)
0.32.2 - January 03, 2024 (16 KB)
0.32.0 - December 28, 2023 (16 KB)
0.31.3 - October 18, 2023 (16 KB)
0.14.0 - September 03, 2019 (8,5 KB)

Toon alle versies (67 totaal)

Runtime afhankelijkheden (5):

rggen-core ~> 0.14

rggen-default-register-map ~> 0.14

rggen-markdown ~> 0.13

rggen-spreadsheet-loader ~> 0.13

rggen-systemverilog ~> 0.14

Development afhankelijkheden (1):

bundler >= 0

Show all transitive dependencies

Eigenaren:

Pushed by:

Authors:

Taichi Ishitani

SHA 256 checksum:

d4dee516c1f51c2cb609296ed62ce807483b263cf0e8ddb1bbdeae0bf2a46b70

Total downloads 88.582

Voor deze versie 1.709

Licentie:
MIT

Required Ruby Version: >= 2.3

New versions require MFA: true

Links:

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