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rggen 0.20.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versies:

  1. 0.28.0 - October 10, 2022 (15,5 KB)
  2. 0.27.2 - August 30, 2022 (15,5 KB)
  3. 0.27.1 - August 21, 2022 (15,5 KB)
  4. 0.27.0 - July 05, 2022 (15,5 KB)
  5. 0.26.2 - June 13, 2022 (15,5 KB)
  6. 0.20.0 - July 06, 2020 (8,5 KB)
Toon alle versies (53 totaal)

Runtime afhankelijkheden (5):

Development afhankelijkheden (1):

Eigenaren:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

de28a102876ba811a5ef55c253a84d38af9a31dd1e707ea0168d659f15ed3570

Total downloads 71.246

Voor deze versie 1.135

Gemfile:
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Installeer:
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Licentie:

MIT

Required Ruby Version: >= 2.4

New versions require MFA: true

Links: