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rggen 0.21.1

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versies:

  1. 0.25.3 - May 17, 2021 (15,5 KB)
  2. 0.25.2 - May 16, 2021 (15,5 KB)
  3. 0.25.1 - March 02, 2021 (9,5 KB)
  4. 0.25.0 - February 28, 2021 (9,5 KB)
  5. 0.24.0 - January 20, 2021 (8,5 KB)
  6. 0.21.1 - July 24, 2020 (8,5 KB)
Toon alle versies (46 totaal)

Runtime afhankelijkheden (5):

Development afhankelijkheden (1):

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Authors:

  • Taichi Ishitani

SHA 256 checksum:

57ddb00f8d0f5b8e3ac875ef3a5d37967a1f50c65dcb5a5181c0f53f316420eb

Total downloads 39.012

Voor deze versie 465

Gemfile:
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Installeer:
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Licentie:

MIT

Required Ruby Version: >= 2.4

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