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rggen 0.27.1

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

版本列表:

  1. 0.29.0 - January 02, 2023 (15.5 KB)
  2. 0.28.0 - October 10, 2022 (15.5 KB)
  3. 0.27.2 - August 30, 2022 (15.5 KB)
  4. 0.27.1 - August 21, 2022 (15.5 KB)
  5. 0.27.0 - July 05, 2022 (15.5 KB)
顯示所有版本(共 54)

Runtime 相依性套件 (6):

Development 相依性套件 (1):

bundler >= 0

擁有者:

Pushed by:

作者:

  • Taichi Ishitani

SHA 256 checksum:

1747831bdde9515b1b1a8a8d7298fe1ed8369b53bd16eb09a72f1f85ef78063e

總下載次數 73,361

這個版本 324

Gemfile:
= 複製 已複製

安裝:
=

License:

MIT

Ruby 版本需求: >= 2.6

New versions require MFA: true

Version published with MFA: true

相關連結: