rggen 0.9.0
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map documents.
Gemfile:
=
instalar:
=
Runtime Dependencies (3):
Development Dependencies (1):
bundler
>= 0
Donos:
Pushed by:
Autores:
-
Taichi Ishitani
SHA 256 checksum:
=