rggen 0.9.0
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map documents.
Gemfile:
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安裝:
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Runtime 相依性套件 (3):
Development 相依性套件 (1):
bundler
>= 0
擁有者:
推送者:
作者:
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Taichi Ishitani
SHA 256 總和檢查碼:
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