Generates a bus-based VHDL IP from a register-map specification. An UART-bus master can be added if needed.

Required Ruby Version

>= 0

Authors

Jean-Christophe Le Lann

Versions

  1. 0.0.6

    1. source

      1. 0.0.6 source May 28, 2020 (22 KB)

Pushed by

jcll

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