Writing portable RTL design in verilog is challenging due to limitations of verilog language. Hence would like to write the leaf modules of the design in verilog but use Ruby to stich different views of the design.

Required Ruby Version

>= 0

Authors

sanjeev singh

Versions

  1. 0.0.2

    1. source

      1. 0.0.2 source March 01, 2015 (37 KB)
  2. 0.0.1

    1. source

      1. 0.0.1 source October 03, 2014 (6.5 KB)

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