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rggen 0.20.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.20.0 - July 06, 2020 (8.5 KB)
  2. 0.19.1 - February 17, 2020 (8.5 KB)
  3. 0.19.0 - February 17, 2020 (8.5 KB)
  4. 0.18.0 - November 19, 2019 (8.5 KB)
  5. 0.17.0 - November 13, 2019 (8.5 KB)
Show all versions (35 total)

Runtime Dependencies (5):

Development Dependencies (1):

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

de28a102876ba811a5ef55c253a84d38af9a31dd1e707ea0168d659f15ed3570

Total downloads 21,840

For this version 115

Gemfile:
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install:
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License:

MIT

Required Ruby Version: >= 2.4

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