RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Required Ruby Version

>= 3.2

Authors

Taichi Ishitani

Versions

  1. 0.36.1

    1. source

      1. 0.36.1 source April 19, 2026 (75.5 KB)
  2. 0.36.0

    1. source

      1. 0.36.0 source January 07, 2026 (75.5 KB)
  3. 0.35.2

    1. source

      1. 0.35.2 source July 21, 2025 (16 KB)
  4. 0.35.1

    1. source

      1. 0.35.1 source June 01, 2025 (16 KB)
  5. 0.35.0

    1. source

      1. 0.35.0 source February 19, 2025 (16 KB)
Show all versions (76 total)

Pushed by

taichi

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