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rggen 0.17.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.27.2 - August 30, 2022 (15.5 KB)
  2. 0.27.1 - August 21, 2022 (15.5 KB)
  3. 0.27.0 - July 05, 2022 (15.5 KB)
  4. 0.26.2 - June 13, 2022 (15.5 KB)
  5. 0.26.1 - June 07, 2022 (15.5 KB)
  6. 0.17.0 - November 13, 2019 (8.5 KB)
Show all versions (52 total)

Development Dependencies (1):

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

58a9f1e33bab6c1b466c19b0c747b57578498c36a5dc589e9c202ab38c99c3bf

Total downloads 66,938

For this version 1,316

Gemfile:
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install:
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License:

MIT

Required Ruby Version: >= 2.3

New versions require MFA: true

Links: