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rggen 0.17.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.25.3 - May 17, 2021 (15.5 KB)
  2. 0.25.2 - May 16, 2021 (15.5 KB)
  3. 0.25.1 - March 02, 2021 (9.5 KB)
  4. 0.25.0 - February 28, 2021 (9.5 KB)
  5. 0.24.0 - January 20, 2021 (8.5 KB)
  6. 0.17.0 - November 13, 2019 (8.5 KB)
Show all versions (46 total)

Development Dependencies (1):

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

58a9f1e33bab6c1b466c19b0c747b57578498c36a5dc589e9c202ab38c99c3bf

Total downloads 36,309

For this version 713

Gemfile:
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install:
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License:

MIT

Required Ruby Version: >= 2.3

Links: