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rggen 0.21.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Gemfile:
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install:
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Versions:

  1. 0.33.1 - January 23, 2024 (16 KB)
  2. 0.33.0 - January 22, 2024 (16 KB)
  3. 0.32.2 - January 03, 2024 (16 KB)
  4. 0.32.0 - December 28, 2023 (16 KB)
  5. 0.31.3 - October 18, 2023 (16 KB)
  6. 0.21.0 - July 22, 2020 (8.5 KB)
Show all versions (67 total)

Runtime Dependencies (5):

Development Dependencies (1):

bundler >= 0

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

c9ac017d4a0629638b0045da55d2702cbfb2eaa44787ee5f7ab1977e3809f475

Total downloads 85,728

For this version 1,261

License:

MIT

Required Ruby Version: >= 2.4

New versions require MFA: true

Links: