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rggen 0.25.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.27.2 - August 30, 2022 (15.5 KB)
  2. 0.27.1 - August 21, 2022 (15.5 KB)
  3. 0.27.0 - July 05, 2022 (15.5 KB)
  4. 0.26.2 - June 13, 2022 (15.5 KB)
  5. 0.26.1 - June 07, 2022 (15.5 KB)
  6. 0.25.0 - February 28, 2021 (9.5 KB)
Show all versions (52 total)

Runtime Dependencies (5):

Development Dependencies (1):

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

fca8089563205d522dc57794f1137d77c39f09224fde72ee10df74b53c35cdbd

Total downloads 65,747

For this version 1,333

Gemfile:
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install:
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License:

MIT

Required Ruby Version: >= 2.5

New versions require MFA: true

Links: