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rggen 0.25.2

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.25.3 - May 17, 2021 (15.5 KB)
  2. 0.25.2 - May 16, 2021 (15.5 KB)
  3. 0.25.1 - March 02, 2021 (9.5 KB)
  4. 0.25.0 - February 28, 2021 (9.5 KB)
  5. 0.24.0 - January 20, 2021 (8.5 KB)
Show all versions (46 total)

Runtime Dependencies (5):

Development Dependencies (1):

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

063142d3a6eddf8d125fccc6f3c60a6a24750c9362cc789b153e18c8811d36bd

Total downloads 32,740

For this version 278

Gemfile:
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install:
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License:

MIT

Required Ruby Version: >= 2.5

Links: