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rggen 0.30.2

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Gemfile:
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Installeer:
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Versies:

  1. 0.35.0 February 19, 2025 (16 KB)
  2. 0.34.0 January 23, 2025 (16 KB)
  3. 0.33.4 November 28, 2024 (16 KB)
  4. 0.33.3 July 20, 2024 (16 KB)
  5. 0.33.2 June 11, 2024 (16 KB)
  6. 0.30.2 August 08, 2023 (16 KB)
Toon alle versies (72 totaal)

Runtime afhankelijkheden (6):

rggen-c-header ~> 0.4.0
rggen-core ~> 0.30.0
rggen-default-register-map ~> 0.30.0
rggen-markdown ~> 0.25.0
rggen-spreadsheet-loader ~> 0.24.0
rggen-systemverilog ~> 0.30.2

Development afhankelijkheden (1):

bundler >= 0
Show all transitive dependencies

Eigenaren:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

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Total downloads 107.235

Voor deze versie 508

Versie vrijgegeven:

Licentie:

MIT

Required Ruby Version: >= 2.7

New versions require MFA: true

Version published with MFA: true

Links:

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