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rggen 0.32.2

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

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Versions:

  1. 0.33.1 - January 23, 2024 (16 KB)
  2. 0.33.0 - January 22, 2024 (16 KB)
  3. 0.32.2 - January 03, 2024 (16 KB)
  4. 0.32.0 - December 28, 2023 (16 KB)
  5. 0.31.3 - October 18, 2023 (16 KB)
Show all versions (67 total)

Runtime Dependencies (6):

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

94c7d09bb80a1073d878898291112390def5eb3bb43147c62e20bf542a4f530c

Total downloads 90,336

For this version 369

License:

MIT

Required Ruby Version: >= 3.0

New versions require MFA: true

Version published with MFA: true

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