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rggen 0.33.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Gemfile:
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installation:
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Versions:

  1. 0.33.1 - January 23, 2024 (16 ko)
  2. 0.33.0 - January 22, 2024 (16 ko)
  3. 0.32.2 - January 03, 2024 (16 ko)
  4. 0.32.0 - December 28, 2023 (16 ko)
  5. 0.31.3 - October 18, 2023 (16 ko)
Voir toutes les versions (67)

Dépendances de Runtime (6):

Propriétaires:

Pushed by:

Auteurs:

  • Taichi Ishitani

Total de contrôle SHA 256:

255e3c96f4dcda4ddd25468d9f9fd7adbe03a322427b923baf7d3876e6f44ee0

Total de téléchargements 91 376

Pour cette version 232

License:

MIT

Version de Ruby requise: >= 3.0

New versions require MFA: true

Version published with MFA: true

Liens: