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rggen 0.11.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map specifications.

Gemfile:
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install:
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Versions:

  1. 0.33.1 - January 23, 2024 (16 KB)
  2. 0.33.0 - January 22, 2024 (16 KB)
  3. 0.32.2 - January 03, 2024 (16 KB)
  4. 0.32.0 - December 28, 2023 (16 KB)
  5. 0.31.3 - October 18, 2023 (16 KB)
  6. 0.11.0 - August 11, 2019 (46.5 KB)
Show all versions (67 total)

Runtime Dependencies (3):

Development Dependencies (1):

bundler >= 0

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

2dcc892f3b7e9c1419431299f4989ee3b3d5b0f21e057d738072f0ecdf328b00

Total downloads 86,794

For this version 1,710

License:

MIT

Required Ruby Version: >= 2.3

New versions require MFA: true

Links: