rggen 0.18.0
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
Gemfile:
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インストール:
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Runtime依存関係 (5):
rggen-core
~> 0.18
rggen-default-register-map
~> 0.18
rggen-markdown
~> 0.15
rggen-spreadsheet-loader
~> 0.14
rggen-systemverilog
~> 0.18
Development依存関係 (1):
bundler
>= 0
所有者:
プッシュ者:
作者:
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Taichi Ishitani
SHA 256チェックサム:
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