rggen 0.25.1
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
Gemfile:
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installation:
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Dépendances de Runtime (5):
rggen-core
~> 0.25.0
rggen-default-register-map
~> 0.25.1
rggen-markdown
~> 0.21.0
rggen-spreadsheet-loader
~> 0.20.0
rggen-systemverilog
~> 0.25.0
Dépendances de Development (1):
bundler
>= 0