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rggen 0.27.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.27.0 - July 05, 2022 (15,5 ko)
  2. 0.26.2 - June 13, 2022 (15,5 ko)
  3. 0.26.1 - June 07, 2022 (15,5 ko)
  4. 0.26.0 - March 25, 2022 (15,5 ko)
  5. 0.25.3 - May 17, 2021 (15,5 ko)
Voir toutes les versions (50)

Dépendances de Runtime (6):

Dépendances de Development (1):

Propriétaires:

Pushed by:

Auteurs:

  • Taichi Ishitani

Total de contrôle SHA 256:

2bb57a4a4e759778549ea6d88075d3b1049bbc59dc3134c98eccef827d2c4988

Total de téléchargements 62 680

Pour cette version 302

Gemfile:
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installation:
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License:

MIT

Version de Ruby requise: >= 2.6

New versions require MFA: true

Version published with MFA: true

Liens: