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rggen 0.27.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

版本列表:

  1. 0.27.0 - July 05, 2022 (15.5 KB)
  2. 0.26.2 - June 13, 2022 (15.5 KB)
  3. 0.26.1 - June 07, 2022 (15.5 KB)
  4. 0.26.0 - March 25, 2022 (15.5 KB)
  5. 0.25.3 - May 17, 2021 (15.5 KB)
顯示所有版本(共 50)

Runtime 相依性套件 (6):

Development 相依性套件 (1):

擁有者:

Pushed by:

作者:

  • Taichi Ishitani

SHA 256 checksum:

2bb57a4a4e759778549ea6d88075d3b1049bbc59dc3134c98eccef827d2c4988

總下載次數 62,281

這個版本 290

Gemfile:
= 複製 已複製

安裝:
=

License:

MIT

Ruby 版本需求: >= 2.6

New versions require MFA: true

Version published with MFA: true

相關連結: