rggen 0.27.0
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
Runtime 相依性套件 (6):
Development 相依性套件 (1):
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作者:
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Taichi Ishitani
SHA 256 checksum:
2bb57a4a4e759778549ea6d88075d3b1049bbc59dc3134c98eccef827d2c4988