rggen 0.10.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map documents.

Gemfile:
= 複製已複製

安裝:
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版本列表:

0.33.1 - January 23, 2024 (16.0 KB)
0.33.0 - January 22, 2024 (16.0 KB)
0.32.2 - January 03, 2024 (16.0 KB)
0.32.0 - December 28, 2023 (16.0 KB)
0.31.3 - October 18, 2023 (16.0 KB)
0.10.0 - July 31, 2019 (44.5 KB)

顯示所有版本（共 67）

Runtime 相依性套件 (3):

rggen-core ~> 0.10

rggen-spreadsheet-loader ~> 0.10

rggen-systemverilog ~> 0.10

Development 相依性套件 (1):

bundler >= 0

Show all transitive dependencies

擁有者:

Pushed by:

作者:

Taichi Ishitani

SHA 256 checksum:

0a304337000817fb2440bece94c66bbed19aaadf53b924437600a6b649658266