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rggen 0.13.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.25.3 - May 17, 2021 (15,5 ko)
  2. 0.25.2 - May 16, 2021 (15,5 ko)
  3. 0.25.1 - March 02, 2021 (9,5 ko)
  4. 0.25.0 - February 28, 2021 (9,5 ko)
  5. 0.24.0 - January 20, 2021 (8,5 ko)
  6. 0.13.0 - August 28, 2019 (8,5 ko)
Voir toutes les versions (46)

Dépendances de Development (1):

Propriétaires:

Pushed by:

Auteurs:

  • Taichi Ishitani

Total de contrôle SHA 256:

6b05e15506b2b5ef2b2a82fcf39b2c7e189facba6ac88844422a9dbc0f9dffb1

Total de téléchargements 38 370

Pour cette version 859

Gemfile:
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installation:
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License:

MIT

Version de Ruby requise: >= 2.3

Liens: