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rggen 0.13.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

版本列表:

  1. 0.25.3 - May 17, 2021 (15.5 KB)
  2. 0.25.2 - May 16, 2021 (15.5 KB)
  3. 0.25.1 - March 02, 2021 (9.5 KB)
  4. 0.25.0 - February 28, 2021 (9.5 KB)
  5. 0.24.0 - January 20, 2021 (8.5 KB)
  6. 0.13.0 - August 28, 2019 (8.5 KB)
顯示所有版本(共 46)

Development 相依性套件 (1):

擁有者:

Pushed by:

作者:

  • Taichi Ishitani

SHA 256 checksum:

6b05e15506b2b5ef2b2a82fcf39b2c7e189facba6ac88844422a9dbc0f9dffb1

總下載次數 38,375

這個版本 859

Gemfile:
= 複製 已複製

安裝:
=

License:

MIT

Ruby 版本需求: >= 2.3

相關連結: