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rggen 0.15.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.28.0 - October 10, 2022 (15.5 KB)
  2. 0.27.2 - August 30, 2022 (15.5 KB)
  3. 0.27.1 - August 21, 2022 (15.5 KB)
  4. 0.27.0 - July 05, 2022 (15.5 KB)
  5. 0.26.2 - June 13, 2022 (15.5 KB)
  6. 0.15.0 - September 18, 2019 (8.5 KB)
Show all versions (53 total)

Development Dependencies (1):

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

62c97c9119f0275d2017019e5a227f824a34ee1752c82cafee45e011a991f124

Total downloads 71,773

For this version 1,487

Gemfile:
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install:
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License:

MIT

Required Ruby Version: >= 2.3

New versions require MFA: true

Links: