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rggen 0.15.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Gemfile:
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install:
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Versions:

  1. 0.31.3 - October 18, 2023 (16 KB)
  2. 0.31.0 - September 12, 2023 (16 KB)
  3. 0.30.2 - August 08, 2023 (16 KB)
  4. 0.30.1 - June 09, 2023 (15.5 KB)
  5. 0.30.0 - April 28, 2023 (15.5 KB)
  6. 0.15.0 - September 18, 2019 (8.5 KB)
Show all versions (62 total)

Runtime Dependencies (5):

Development Dependencies (1):

bundler >= 0

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

62c97c9119f0275d2017019e5a227f824a34ee1752c82cafee45e011a991f124

Total downloads 81,627

For this version 1,620

License:

MIT

Required Ruby Version: >= 2.3

New versions require MFA: true

Links: