rggen 0.15.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Gemfile:
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installation:
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Versions:

0.33.1 - January 23, 2024 (16 ko)
0.33.0 - January 22, 2024 (16 ko)
0.32.2 - January 03, 2024 (16 ko)
0.32.0 - December 28, 2023 (16 ko)
0.31.3 - October 18, 2023 (16 ko)
0.15.0 - September 18, 2019 (8,5 ko)

Voir toutes les versions (67)

Dépendances de Runtime (5):

rggen-core ~> 0.15

rggen-default-register-map ~> 0.15

rggen-markdown ~> 0.14

rggen-spreadsheet-loader ~> 0.14

rggen-systemverilog ~> 0.15

Dépendances de Development (1):

bundler >= 0

Show all transitive dependencies

Propriétaires:

Pushed by:

Auteurs:

Taichi Ishitani

Total de contrôle SHA 256:

62c97c9119f0275d2017019e5a227f824a34ee1752c82cafee45e011a991f124

Total de téléchargements 88 437

Pour cette version 1 688

License:
MIT

Version de Ruby requise: >= 2.3

New versions require MFA: true

Liens:

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