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rggen 0.15.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Gemfile:
= 複製 已複製

安裝:
=

版本列表:

  1. 0.33.1 - January 23, 2024 (16.0 KB)
  2. 0.33.0 - January 22, 2024 (16.0 KB)
  3. 0.32.2 - January 03, 2024 (16.0 KB)
  4. 0.32.0 - December 28, 2023 (16.0 KB)
  5. 0.31.3 - October 18, 2023 (16.0 KB)
  6. 0.15.0 - September 18, 2019 (8.5 KB)
顯示所有版本(共 67)

Runtime 相依性套件 (5):

Development 相依性套件 (1):

bundler >= 0

擁有者:

Pushed by:

作者:

  • Taichi Ishitani

SHA 256 checksum:

62c97c9119f0275d2017019e5a227f824a34ee1752c82cafee45e011a991f124

總下載次數 86,130

這個版本 1,669

License:

MIT

Ruby 版本需求: >= 2.3

New versions require MFA: true

相關連結: