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rggen 0.16.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.25.3 - May 17, 2021 (15,5 ko)
  2. 0.25.2 - May 16, 2021 (15,5 ko)
  3. 0.25.1 - March 02, 2021 (9,5 ko)
  4. 0.25.0 - February 28, 2021 (9,5 ko)
  5. 0.24.0 - January 20, 2021 (8,5 ko)
  6. 0.16.0 - October 01, 2019 (8,5 ko)
Voir toutes les versions (46)

Dépendances de Development (1):

Propriétaires:

Pushed by:

Auteurs:

  • Taichi Ishitani

Total de contrôle SHA 256:

569040780c37e1f8bf6409cdff0258d29b9e56d5cb501910e003d0dde1f0130e

Total de téléchargements 38 672

Pour cette version 853

Gemfile:
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installation:
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License:

MIT

Version de Ruby requise: >= 2.3

Liens: