rggen 0.16.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Gemfile:
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Versões:

0.33.1 - January 23, 2024 (16 KB)
0.33.0 - January 22, 2024 (16 KB)
0.32.2 - January 03, 2024 (16 KB)
0.32.0 - December 28, 2023 (16 KB)
0.31.3 - October 18, 2023 (16 KB)
0.16.0 - October 01, 2019 (8,5 KB)

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Runtime Dependencies (5):

rggen-core ~> 0.16

rggen-default-register-map ~> 0.16

rggen-markdown ~> 0.15

rggen-spreadsheet-loader ~> 0.14

rggen-systemverilog ~> 0.16

Development Dependencies (1):

bundler >= 0

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Donos:

Pushed by:

Autores:

Taichi Ishitani

SHA 256 checksum:

569040780c37e1f8bf6409cdff0258d29b9e56d5cb501910e003d0dde1f0130e

Total de downloads 89.564

Desta versão 1.702

Licença:
MIT

Versão Requerida do Ruby: >= 2.3

New versions require MFA: true

Links:

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