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rggen 0.20.0

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.28.0 - October 10, 2022 (15,5 ko)
  2. 0.27.2 - August 30, 2022 (15,5 ko)
  3. 0.27.1 - August 21, 2022 (15,5 ko)
  4. 0.27.0 - July 05, 2022 (15,5 ko)
  5. 0.26.2 - June 13, 2022 (15,5 ko)
  6. 0.20.0 - July 06, 2020 (8,5 ko)
Voir toutes les versions (53)

Dépendances de Runtime (5):

Dépendances de Development (1):

Propriétaires:

Pushed by:

Auteurs:

  • Taichi Ishitani

Total de contrôle SHA 256:

de28a102876ba811a5ef55c253a84d38af9a31dd1e707ea0168d659f15ed3570

Total de téléchargements 71 650

Pour cette version 1 142

Gemfile:
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installation:
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License:

MIT

Version de Ruby requise: >= 2.4

New versions require MFA: true

Liens: