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rggen 0.27.2

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.28.0 - October 10, 2022 (15.5 KB)
  2. 0.27.2 - August 30, 2022 (15.5 KB)
  3. 0.27.1 - August 21, 2022 (15.5 KB)
  4. 0.27.0 - July 05, 2022 (15.5 KB)
  5. 0.26.2 - June 13, 2022 (15.5 KB)
Show all versions (53 total)

Runtime Dependencies (6):

Development Dependencies (1):

Owners:

Pushed by:

Authors:

  • Taichi Ishitani

SHA 256 checksum:

fa641f58e8ee807c5dffc3979e1d7ac14d0061a5ddfd7e3ecbea18d975ed12b9

Total downloads 71,246

For this version 369

Gemfile:
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install:
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License:

MIT

Required Ruby Version: >= 2.6

New versions require MFA: true

Version published with MFA: true

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