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rggen 0.27.2

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.

Versions:

  1. 0.29.0 - January 02, 2023 (15,5 ko)
  2. 0.28.0 - October 10, 2022 (15,5 ko)
  3. 0.27.2 - August 30, 2022 (15,5 ko)
  4. 0.27.1 - August 21, 2022 (15,5 ko)
  5. 0.27.0 - July 05, 2022 (15,5 ko)
Voir toutes les versions (54)

Dépendances de Runtime (6):

Dépendances de Development (1):

bundler >= 0

Propriétaires:

Pushed by:

Auteurs:

  • Taichi Ishitani

Total de contrôle SHA 256:

fa641f58e8ee807c5dffc3979e1d7ac14d0061a5ddfd7e3ecbea18d975ed12b9

Total de téléchargements 73 361

Pour cette version 418

Gemfile:
= Copier Copié!

installation:
=

License:

MIT

Version de Ruby requise: >= 2.6

New versions require MFA: true

Version published with MFA: true

Liens: