rggen 0.12.0
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
Gemfile:
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安装:
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Runtime 依赖 (4):
rggen-core
~> 0.12
rggen-markdown
~> 0.12
rggen-spreadsheet-loader
~> 0.10
rggen-systemverilog
~> 0.11
Development 依赖 (1):
bundler
>= 0