rggen 0.9.0
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map documents.
Gemfile:
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installation:
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Dépendances de Runtime (3):
Dépendances de Development (1):
bundler
>= 0
Propriétaires:
Pushed by:
Auteurs:
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Taichi Ishitani
Total de contrôle SHA 256:
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