rggen 0.9.0
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map documents.
Gemfile:
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安装:
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Runtime 依赖 (3):
Development 依赖 (1):
bundler
>= 0
所有者:
推送者:
作者:
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Taichi Ishitani
SHA 256 校验和:
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